In digital data communication and storage systems, it is desirable to maintain the integrity of data throughout the entire data communication path; that is, from the moment data passes from the host or transmission source until it is safely received or stored, as well as in the reverse path back to the host or source. With respect to magnetic recording systems, in addition to providing a reliable read/write process to and from a degrading storage medium, such as a magnetic storage disk, the probability of reliable data transfer can be enhanced by providing error control over the entire read/write path, including intermediate points in the data path that are not protected by conventional ECC strategies.
Error detection and correction techniques typically rely on the use of some form of overhead redundancy that is appended to blocks of data during an encoding process to facilitate detection and correction of errors that occur during transmission of the block through a noisy data channel. The appended redundant information is typically generated from, and thus dependent upon, the precise bit pattern of the data block to be protected. When the encoded data blocks are received, the reliability of the transmission process may be checked by regenerating the redundant information from the received data block (using the same coding algorithm that was used to generate the redundancy information prior to transmission) and comparing the regenerated information with that which was originally appended. If the appended redundancy does not match the regenerated redundancy one or more data errors are assumed to have occurred. When this happens, a request can be made to either retransmit or reread the data or, in the case of codes having error correction capabilities, to locate and physically correct the data errors.
In modern magnetic storage systems, a main error correction code ("ECC") and implementing circuitry is typically used to detect and correct errors in data blocks that occur during the processes of reading and writing data to and from a storage surface of the magnetic medium itself. A cross-check code, which typically utilizes a different encoding algorithm from the ECC, has been used to check that any corrections carried out by the ECC are properly performed. An example of a disk drive data storage system that uses ECC and cross-check codes to perform on-the-fly error checking and correction is disclosed in commonly assigned U.S. Pat. No. 5,241,546 to Peterson et al., entitled "On-The-Fly Error Correction With Embedded Digital Controller." In commonly assigned U.S. Pat. No. 5,422,895, to Nguyen et al., entitled "Cross-Checking For On-The-Fly Reed-Solomon Error Correction Code," an improved cross-checking code and strategy is disclosed. As described in these patents, the disclosure of which is hereby incorporated by reference, the combination of ECC with cross-checking reduces the statistical probability of ECC miscorrection for a given ECC coding strategy. These ECC and cross-check codes, however, are limited in operation to the detection and correction of errors that are associated with the storage of information on the data degrading magnetic storage medium.
Accordingly, the chances of delivering error free data may be enhanced by extending error control to other parts of the data channel that are not protected by the main ECC and cross-check codes. In order to protect data from the moment it leaves the host until the time it is encoded (and hence protected) by the main ECC encoder/decoder ("ENDEC") prior to being written onto the storage medium, it is necessary to utilize additional coding strategies. Similarly, the data path back to the host from the storage medium should also be protected. Codes used to detect errors that occur on those portions of the data path, outside the protection of the ECC and cross-check codes are referred to herein as data integrity codes.
In the past, simple parity check codes or cyclical redundancy codes ("CRC") have been employed to protect data temporarily stored in a block memory buffer located in a data path between the host interface and the ECC circuitry. These codes typically involve appending a single parity bit to each byte of data with the state of the parity bit (i.e., "1" or "0") dependent on the data byte to be protected and the particular parity code used. With "odd" and "even" parity schemes, the parity bit is determined by adding up the number of "1's" (accomplished in practice by XORing consecutive bits) in the data symbol and appending either a "1" or a "0" to the symbol such that the total number of "1's" is either odd, in the case of odd parity, or even, in the case of even parity.
However, a well known weakness in parity codes is that they can only reliably detect single bit errors within a data symbol or block protected by the parity bit whereas multiple bit errors that offset each other with respect to the chosen parity go undetected. Moreover, since most RAM manufacturers no longer plan to supply 9 bit wide or 18 bit wide RAM chips, there is no longer data space available in the block buffer memory, typically a Dynamic Random Access Memory ("DRAM") store, to accommodate an extra parity bit. Thus, not only is there a need for a more powerful alternative to the simple parity check codes, but the ability to use these codes as a data integrity code in magnetic recording and other data communications systems employing RAM buffer memories is rapidly fading.
Cyclical redundancy codes offer an improvement over single bit parity codes in that they have the ability to detect multiple bit errors within a protected symbol or entire block of data. These codes are derived from some higher order combinations of bits within the symbol or block and may have multiple bits of redundancy. However, the use of a CRC to protect data in the block buffer memory involves adding CRC circuitry on both sides of the buffer.
As discussed above, error corrections made in accordance with the ECC may be cross-checked by a cross-check code to increase the overall reliability of the error correction process. The cross-check code disclosed in U.S. Pat. No. 5,422,895 to Nguyen et al. is a Reed-Solomon code that offers greatly increased error detection capabilities over traditional parity check and CRC codes.
Accordingly, it would be desirable to provide a system architecture that utilizes the existing cross-check code and hardware as a data integrity code to provide a more powerful alternative to existing buffer protection strategies. Such an architecture would constitute a major improvement over prior art parity check and CRC codes inasmuch as a more powerful data integrity strategy could be provided with minimal additional hardware.